Preface ........................................................ xv
Content overview ............................................. xvii
Feedback ....................................................... xx
Acknowledgments ................................................ xx
List of Figures ............................................. xxiii
List of Tables ................................................. li
1 Mixed-Signal Integrated Systems: Limitations and
Challenges ................................................... 1
1.1 Integrated circuit design flow .......................... 2
1.2 Design technique issues ................................. 6
1.3 Integrated system perspectives .......................... 7
1.4 Built-in self-test structures ........................... 8
1.5 Concluding remarks ...................................... 9
1.6 To probe further ........................................ 9
2 MOS Transistors ............................................. 11
2.1 Transistor structure ................................... 12
2.1.1 I/V characteristics of MOS transistors .......... 13
2.1.2 Drain current in the strong inversion
approximation ................................... 14
2.1.3 Drain current in the subthreshold region ........ 17
2.1.4 MOS transistor capacitances ..................... 20
2.1.5 Scaling effects on MOS transistors .............. 21
2.2 Transistor SPICE models ................................ 23
2.2.1 Electrical characteristics ...................... 23
2.2.2 Temperature effects ............................. 27
2.2.3 Noise models .................................... 28
2.3 Summary ................................................ 31
2.4 Circuit design assessment .............................. 32
Bibliography ................................................ 37
3 Physical Design of MOS Integrated Circuits .................. 39
3.1 MOS Transistors ........................................ 40
3.2 Passive components ..................................... 41
3.2.1 Capacitors ...................................... 42
3.2.2 Resistors ....................................... 43
3.2.3 Inductors ....................................... 44
3.3 Integrated-circuit (IС) interconnects .................. 46
3.4 Physical design considerations ......................... 48
3.5 1С packaging ........................................... 53
3.6 Summary ................................................ 53
3.7 Circuit design assessment .............................. 53
Bibliography ................................................ 57
4 Bias and Current Reference Circuits ......................... 59
4.1 Current mirrors ........................................ 60
4.1.1 Simple current mirror ........................... 60
4.1.2 Cascode current mirror .......................... 62
4.1.3 Low-voltage active current mirror ............... 75
4.2 Current and voltage references ......................... 76
4.2.1 Supply-voltage independent current reference .... 78
4.2.2 Bandgap references .............................. 79
4.2.2.1 Low-voltage bandgap voltage reference .. 82
4.2.2.2 Curvature-compensated bandgap voltage
reference .............................. 83
4.2.3 Floating-gate voltage reference ................. 86
4.3 Summary ................................................ 87
4.4 Circuit design assessment .............................. 87
Bibliography ................................................ 93
5 CMOS Amplifiers ............................................. 95
5.1 Differential amplifier ................................. 96
5.1.1 Dynamic range ................................... 97
5.1.2 Source-coupled differential transistor pair ..... 99
5.1.3 Current mirror ................................. 101
5.1.4 Slew-rate limitation ........................... 102
5.1.5 Small-signal characteristics ................... 103
5.1.6 Offset voltage ................................. 108
5.1.7 Noise in a differential transistor pair ........ 110
5.1.8 Operational amplifier .......................... Ill
5.2 Linearization techniques for transconductors .......... 114
5.3 Single-stage amplifier ................................ 129
5.4 Folded-cascode amplifier .............................. 130
5.5 Fully differential amplifier architectures ............ 135
5.5.1 Fully differential folded-cascode amplifier .... 135
5.5.1.1 Basic structure ....................... 135
5.5.1.2 Gain-enhanced structure ............... 138
5.5.2 Telescopic amplifier ........................... 143
5.5.3 Common-mode feedback circuits .................. 146
5.5.3.1 Continuous-time common-mode
feedback circuit ...................... 146
5.5.3.2 Switched-capacitor common-mode
feedback circuit ...................... 150
5.5.4 Pseudo fully differential amplifier ............ 154
5.6 Multi-stage amplifier structures ...................... 156
5.6.1 Output stage ................................... 157
5.6.2 Two-stage amplifier ............................ 167
5.6.3 Optimization of a two-pole amplifier for fast
settling response .............................. 174
5.6.4 Three-stage amplifier .......................... 177
5.7 Rail-to-rail amplifiers ............................... 186
5.7.1 Amplifier with a class AB input stage .......... 187
5.7.2 Two-stage amplifier with class AB output
stage ......................................... 189
5.7.3 Amplifier with rail-to-rail input and output
stages ........................................ 190
5.8 Amplifier characterization ............................ 194
5.8.1 Finite gain and bandwidth ...................... 194
5.8.2 Phase margin ................................... 195
5.8.3 Input and output impedances .................... 195
5.8.4 Power supply rejection ......................... 195
5.8.5 Slew rate ...................................... 195
5.8.6 Low-frequency noise and dc offset voltage ...... 196
5.8.6.1 Auto-zero compensation scheme ......... 198
5.8.6.2 Chopper technique ..................... 201
5.9 Summary ............................................... 204
5.10 Circuit design assessment ............................. 204
Bibliography ............................................... 219
6 Nonlinear Analog Components ................................ 225
6.1 Comparators ........................................... 226
6.1.1 Amplifier-based comparator ..................... 226
6.1.2 Comparator using charge balancing
techniques ..................................... 233
6.1.3 Latched comparators ............................ 234
6.1.3.1 Static comparator ..................... 235
6.1.3.2 Dynamic comparator .................... 239
6.2 Multipliers ........................................... 242
6.2.1 Multiplier cores ............................... 244
6.2.1.1 Multiplier core based on
externally controlled
transconductances ..................... 244
6.2.1.2 Multiplier core based on the
quarter-square technique .............. 249
6.2.1.3 Design issues ......................... 255
6.2.2 Design examples ............................... 256
6.3 Summary ............................................... 259
6.4 Circuit design assessment ............................. 259
Bibliography ............................................... 265
7 Continuous-Time Circuits ................................... 269
7.1 Wireless communication system ......................... 270
7.1.1 Receiver and transmitter architectures ......... 272
7.1.2 Frequency translation and quadrature
multiplexing ................................... 275
7.1.3 Architecture of a harmonic-rejection
transceiver .................................... 281
7.1.4 Amplifiers ..................................... 282
7.1.4.1 Power amplifier ....................... 283
7.1.4.2 Low-noise amplifier ................... 292
7.1.5 Mixer .......................................... 302
7.1.6 Voltage-controlled oscillator .................. 306
7.1.7 Automatic gain control ......................... 321
7.2 Continuous-time filters ............................... 324
7.2.1 RC circuits .................................... 326
7.2.2 MOSFET-C circuits .............................. 327
7.2.3 gm-C circuits .................................. 330
7.2.4 gm-C operational amplifier (OA) circuits ....... 331
7.2.5 Summer circuits ................................ 335
7.2.6 Gyrator ........................................ 336
7.3 Filter characterization ............................... 337
7.4 Filter design methods ................................. 338
7.4.1 First-order filter design ...................... 340
7.4.2 Biquadratic filter design methods .............. 342
7.4.2.1 Signal-flow graph-based design ........ 342
7.4.2.2 Gyrator-based design .................. 346
7.4.3 Ladder filter design methods ................... 349
7.4.3.1 LC ladder network-based design ........ 349
7.4.3.2 Signal-flow graph-based design ........ 352
7.5 Design considerations for continuous-time filters ..... 356
7.5.1 Automatic on-chip tuning of continuous-time
filters ........................................ 356
7.5.2 Nonideal integrator ............................ 358
7.6 Frequency-control systems ............................. 359
7.6.1 Phase-locked-loop-based technique ............. 359
7.6.1.1 Operation principle .................. 359
7.6.1.2 Architecture of the master: VCO or
VCF ................................. 360
7.6.1.3 Phase detector ....................... 361
7.6.1.4 Implementation issues ................ 362
7.6.2 Charge comparison-based technique ............. 363
7.7 Quality-factor and bandwidth control systems .......... 365
7.7.1 Magnitude-locked-loop-based technique .......... 365
7.7.2 Envelope detection-based technique ............. 366
7.8 Practical design considerations ....................... 369
7.9 Other tuning strategies ............................... 372
7.9.1 Tuning scheme using an external resistor ....... 372
7.9.2 Self-tuned filter ............................. 373
7.9.3 Tuning scheme based on adaptive filter
technique ...................................... 375
7.10 Summary ............................................... 378
7.11 Circuit design assessment ............................. 378
Bibliography ............................................... 395
8 Switched-Capacitor Circuits ................................ 403
8.1 Anti-aliasing filter .................................. 404
8.2 Capacitors ............................................ 406
8.3 Switches .............................................. 407
8.3.1 Switch description ............................. 407
8.3.2 Switch error sources ........................... 409
8.3.3 Switch compensation techniques ................. 413
8.4 Programmable capacitor arrays ......................... 414
8.5 Operational amplifiers ................................ 416
8.6 Track-and-hold (T/H) and sampk>and-hold (S/H)
circuits ............................................. 417
8.7 Switched-capacitor (SC) circuit principle ............. 425
8.8 SC filter design ...................................... 430
8.8.1 First-order filter ............................. 432
8.8.2 Biquad filter .................................. 433
8.8.3 Ladder filter .................................. 441
8.9 SC ladder filter based on the LDI transform ........... 441
8.10 SC ladder filter based on the bilinear transform ...... 449
8.10.1 RLC filter prototype-based design .............. 449
8.10.2 Transfer function-based design of allpass
filters ........................................ 456
8.11 Effects of the amplifier finite gain and bandwidth .... 459
8.11.1 Amplifier dc gain .............................. 461
8.11.2 Amplifier finite bandwidth ..................... 463
8.11.2.1 Inverting integrator .................. 463
8.11.2.2 Noninverting integrator ............... 465
8.12 Settling time in the integrator ....................... 466
8.13 Amplifier dc offset voltage limitations ............... 469
8.14 Computer-aided analysis of SC circuits ................ 469
8.15 T/H and S/H circuits based on SC circuit
principle ............................................. 473
8.16 Circuit structures with low sensitivity to
nonidealities ......................................... 478
8.16.1 Integrators .................................... 479
8.16.2 Gain stages .................................... 485
8.17 Low-voltage SC circuits ............................... 489
8.18 Summary ............................................... 492
8.19 Circuit design assessment ............................. 493
Bibliography ............................................... 503
9 Data Converter Principles .................................. 509
9.1 Binary codes .......................................... 512
9.1.1 Unipolar codes ................................. 513
9.1.2 Bipolar codes .................................. 515
9.1.3 Remarks ........................................ 516
9.2 Data converter characterization ....................... 516
9.2.1 Quantization errors ............................ 516
9.2.2 Errors related to circuit components ........... 521
9.2.3 Static errors .................................. 523
9.2.4 Dynamic errors ................................. 526
9.3 Summary ............................................... 529
Bibliography ............................................... 531
10 Nyquist Digital-to-Analog Converters ....................... 533
10.1 Digital-to-analog converter (DAC) architectures ....... 534
10.1.1 Binary-weighted structure ...................... 534
10.1.2 Thermometer-coded structure .................... 534
10.1.3 Segmented architecture ......................... 535
10.2 Voltage-scaling DACs .................................. 535
10.2.1 Basic resistor-string DAC ...................... 535
10.2.2 Intermeshed resistor-string DAC ................ 541
10.2.3 Two-stage resistor-string DAC .................. 542
10.3 Current-scaling DACs .................................. 545
10.3.1 Binary-weighted resistor DAC ................... 545
10.3.2 R-2R ladder DAC ................................ 547
10.3.3 Switched-current DAC ........................... 547
10.4 Charge-scaling DAC .................................... 554
10.5 Hybrid DAC ............................................ 557
10.6 Configuring a unipolar DAC for the bipolar
conversion ........................................... 562
10.7 Algorithmic DAC ....................................... 564
10.8 Summary ............................................... 565
10.9 Circuit design assessment ............................. 566
Bibliography ............................................... 571
11 Nyquist Analog-to-Digital Converters ....................... 573
11.1 Analog-to-digital converter (ADC) architectures ....... 574
11.1.1 Successive approximation register ADC .......... 574
11.1.2 Integrating ADC ................................ 584
11.1.3 Flash ADC ...................................... 592
11.1.4 Averaging ADC .................................. 604
11.1.5 Folding and interpolating ADC .................. 607
11.1.6 Sub-ranging ADC ................................ 619
11.1.7 Pipelined ADC .................................. 619
11.1.8 Algorithmic ADC ................................ 632
11.1.9 Time-interleaved ADC ........................... 635
11.2 Summary ............................................... 639
11.3 Circuit design assessment ............................. 640
Bibliography ............................................... 647
12 Delta-Sigma Data Converters ................................ 651
12.1 Delta-sigma analog-to-digital converter ............... 652
12.1.1 Time domain behavior ........................... 653
12.1.2 Linear model of a discrete-time modulator ...... 655
12.1.3 Modulator dynamic range ........................ 657
12.1.4 Continuous-time modulator ...................... 661
12.1.5 Lowpass delta-sigma modulator .................. 664
12.1.5.1 Single-stage modulator with a 1-bit
quantizer ............................. 664
12.1.5.2 Dithering ............................. 668
12.1.5.3 Design examples ....................... 668
12.1.5.4 Modulator architectures with
a multi-bit quantizer ................. 673
12.1.5.5 Cascaded modulator .................... 676
12.1.5.6 Effect of the multi-bit DAC
nonlinearity .......................... 686
12.1.5.7 Quantization noise shaping and inter
-stage coefficient scaling ............ 686
12.1.6 Bandpass delta-sigma modulator ................. 688
12.1.6.1 Single-loop bandpass delta-sigma
modulator ............................. 688
12.1.6.2 Cascaded bandpass delta-sigma
modulator ............................. 689
12.1.6.3 Design examples ....................... 690
12.1.7 Decimation filter .............................. 697
12.2 Delta-sigma digital-to-analog converter ............... 717
12.2.1 Interpolation filter ........................... 718
12.2.2 Digital modulator .............................. 725
12.3 Nyquist DAC design issues ............................. 729
12.3.1 Data-weighted averaging technique .............. 730
12.3.2 Element selection logic based on a tree
structure and butterfly shuffler .............. 731
12.3.3 Vector feedback DEM DAC ........................ 734
12.4 Data converter testing and characterization ........... 739
12.4.1 Histogram-based testing ........................ 740
12.4.2 Spectral analysis method ....................... 742
12.4.3 Walsh transform-based transfer function
estimation ..................................... 744
12.4.4 Testing using sine-fit algorithms .............. 744
12.5 Delta-sigma modulator-based oscillator ................ 745
12.6 Digital signal processor interfacing with data
converters ............................................ 748
12.6.1 Parallel interfacing ........................... 751
12.6.2 Serial interfacing ............................. 752
12.7 Built-in self-test structures for data converters .... 753
12.8 Circuit design assessment ............................. 756
Bibliography ............................................... 765
13 Circuits for Clock Signal Generation and Synchronization ... 769
13.1 Generation of clock signals with nonoverlapping
phases ................................................ 770
13.2 Phase-locked loop ..................................... 773
13.2.1 PLL linear model ............................... 773
13.2.2 Charge-pump PLL ................................ 774
13.3 Charge-pump PLL building blocks ....................... 775
13.3.1 Phase and frequency detector ................... 775
13.3.2 Phase detector ................................. 778
13.3.2.1 Linear phase detector ................. 778
13.3.2.2 Binary phase detector ................. 779
13.3.2.3 Half-rate phase detector .............. 780
13.3.3 Charge-pump circuit ............................ 783
13.3.4 Loop filter .................................... 786
13.3.5 Voltage-controlled oscillator .................. 788
13.4 Applications .......................................... 792
13.4.1 Frequency synthesizer .......................... 792
13.4.2 Clock and data recovery ............................. 802
13.5 Delay-locked loop ..................................... 805
13.6 PLL with a built-in self-test structure ............... 807
13.7 PLL specifications .................................... 808
13.8 Summary ............................................... 810
13.9 Circuit design assessment ............................. 810
Bibliography ............................................... 817
Appendix A Logic Building Blocks .............................. 821
A.l Boolean algebra ....................................... 821
A.1.1 Basic operations ............................... 821
A.1.2 Exclusive-OR and equivalence operations ........ 822
A.2 Combinational logic circuits .......................... 822
A.2.1 Basic gates .................................... 822
A.2.2 CMOS implementation ............................ 824
А.З Sequential logic circuits .............................. 827
A.3.1 Asynchronous SR latch .......................... 828
A.3.2 Asynchronous SR latch .......................... 828
A.3.3 D latch ........................................ 829
A.3.4 D flip-flops ................................... 829
A.3.5 CMOS implementation ........................... 831
A.4 Bibliography .......................................... 834
Appendix В Transistor sizing in building blocks ............... 837
B.l MOS transistor ........................................ 837
B.2 Amplifier ............................................. 842
B.3 Comparator and latch .................................. 851
B.4 Bibliography .......................................... 854
Appendix С Signal-Flow Graph .................................. 855
C.I SFG reduction rules ................................... 856
C.2 Mason's gain formula ................................. 857
C.3 Bibliography .......................................... 860
Index ........................................................ 861
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