 | Stanisavljević M. Reliability of nanoscale circuits and systems: methodologies and circuit architectures / M.Stanisavljević, A.Schmid, Y.Leblebici. - New York: Springer, 2011. - xxvii, 195 p.: ill. - Ref.: p.177-190. - Ind.: p.191-195. - ISBN 978-1-4419-6216-4
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1 Introduction ................................................. 1
1.1 From Microelectronics to Nanoelectronics ................ 1
1.2 Issues Related to Reliable Design ....................... 5
1.3 Outline of the Book ..................................... 6
2 Reliability, Faults, and Fault Tolerance ..................... 7
2.1 Reliability and Fault Tolerance ......................... 7
2.2 Faults and Fault Models ................................ 10
2.3 Transistor Fault Model ................................. 13
3 Nanotechnology and Nanodevices .............................. 19
3.1 Single-Electron Transistors (SETs) ..................... 21
3.2 Resonant Tunneling Devices (RTDs) ...................... 23
3.3 Quantum Cellular Automata (QCA) ........................ 24
3.4 One-Dimensional (ID) Devices ........................... 25
3.5 CMOS-Molecular Electronics (CMOL) ...................... 27
3.6 Other Nanoelectronic Devices ........................... 28
3.7 Overview of Nanodevices' Characteristics ............... 29
3.8 Challenges for Designing System Architectures Based
on Nanoelectronic Devices .............................. 32
4 Fault-Tolerant Architectures and Approaches ................. 35
4.1 Static Redundancy ...................................... 36
4.1.1 Hardware Redundancy ............................. 36
4.1.2 Time Redundancy ................................. 41
4.1.3 Information Redundancy .......................... 41
4.1.4 Hybrid Approaches ............................... 42
4.1.5 Recent Techniques ............................... 43
4.2 Dynamic Redundancy ..................................... 43
4.2.1 Reconfiguration ................................. 44
4.3 Overview of the Presented Fault-Tolerant Techniques .... 46
5 Reliability Evaluation Techniques ........................... 49
5.1 Historically Important Tools ........................... 51
5.2 Most Recent Progress in Reliability Evaluation ......... 53
5.3 Monte Carlo Reliability Evaluation Tool ................ 57
5.4 Summary ................................................ 61
6 Averaging Design Implementations ............................ 63
6.1 The Averaging Technique ................................ 63
6.1.1 Feed-Forward ANN Boolean Function Synthesis
Block ........................................... 64
6.1.2 Four-Layer Reliable Architecture (4LRA) ......... 66
6.1.3 Hardware Realizations of Averaging and
Thresholding .................................... 68
6.1.4 Examples of Four-Layer Reliable Architecture
Transfer Function Surfaces ...................... 70
6.2 Assessment of the Reliability of Gates and Small
Blocks ................................................. 76
6.2.1 Comparative Analysis of Obtained Results ........ 77
6.3 Differential Signaling for Reliability Improvement ..... 81
6.3.1 Fault-Tolerant Properties of Differential
Signaling ....................................... 81
6.3.2 Comparative Analysis of Obtained Results ........ 82
6.4 Reliability of SET Systems ............................. 85
6.4.1 Reliability Evaluation .......................... 86
6.4.2 Comparison of Different Fault-Tolerant
Techniques ...................................... 89
6.5 Summary ................................................ 92
7 Statistical Evaluation of Fault Tolerance Using
Probability Density Functions ............................... 93
7.1 Statistical Method for the Analysis of Fault-Tolerant
Techniques ............................................. 94
7.2 Advanced Single-Pass Reliability Evaluation Method .... 103
7.2.1 Modified Single-Pass Reliability Evaluation
Tool ........................................... 104
7.2.2 Output PDF Modeling ............................ 112
7.3 Conclusions ........................................... 118
8 Design Methodology: Reliability Evaluation and
Optimization ............................................... 121
8.1 Local-Level Reliability Evaluation .................... 123
8.1.1 Dependency of Reliability on Logic Depth ....... 125
8.1.2 Reliability Improvement by Logic Depth
Reduction ...................................... 127
8.1.3 Reliability Improvement of Different Fault-
Tolerant Techniques ............................ 128
8.2 Optimal Reliability Partitioning ...................... 134
8.2.1 Partitioning to Small and Mid-Sized
Partitions ..................................... 136
8.2.2 Partitioning to Large-Sized Partitions ......... 138
8.3 System-Level Evaluation and Optimization .............. 139
8.3.1 R-Fold Modular Redundancy (RMR) ................ 145
8.3.2 Cascaded R-Fold Modular Redundancy (CRMR) ...... 151
8.3.3 Distributed R-Fold Modular Redundancy (DRMR) ... 155
8.3.4 NAND Multiplexing .............................. 161
8.3.5 Chip-Level Analysis ............................ 163
8.4 Conclusions ........................................... 165
9 Summary and Conclusions .................................... 167
9.1 Reliability-Aware Design Methodology .................. 167
9.2 Conclusions or Back into the Big Picture .............. 169
A Probability of Chip and Signal Failure in System-Level
Optimizations .............................................. 171
A.l Probability of Chip Failure for Cascaded R-Fold
Modular Redundancy Architecture ....................... 171
A.1.1 Generalization ................................. 174
A.2 Probability of Input Signals Failure in Distributed
R-Fold Modular Redundancy Architecture ................ 175
References ................................................. 177
Index ......................................................... 191
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