Integrated power devices and TCAD simulation (Boca Raton, 2014). - ОГЛАВЛЕНИЕ / CONTENTS

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ОбложкаIntegrated power devices and TCAD simulation / Y.Fu, Z.Li, Wai Tung Ng, J.K.O.Sin. - Boca Raton: CRC/Taylor & Francis, 2014. - xvii, 338 p.: ill. - (Devices, circuits, and systems). - Bibliogr.: p.323-330. - Ind.: p.331-338. - ISBN 978-1-4665-8381-8
 

Место хранения: 02 | Отделение ГПНТБ СО РАН | Новосибирск

Оглавление / Contents
 
Preface ........................................................ xv
About the Authors ............................................ xvii

Chapter 1   Power Electronics, the Enabling Green Technology .... 1
1.1  Introduction to Power Electronics .......................... 1
1.2  History of Power Electronics ............................... 3
1.3  DC/DC Converters ........................................... 4
1.4  Linear Voltage Regulators .................................. 4
1.5  Switched Capacitor DC/DC Converters (Charge Pumps) ......... 5
1.6  Switched Mode DC/DC Converters ............................. 7
1.7  Comparison between Linear Regulators, Charge Pumps, and
     Switched Regulators ........................................ 8
1.8  Topologies for Nonisolated DC/DC Switched Converters ....... 9
     1.8.1  Buck Converter ...................................... 9
     1.8.2  Boost Converter .................................... 11
     1.8.3  Buck-Boost Converter ............................... 13
     1.8.4  Cuk Converter ...................................... 14
     1.8.5  Additional Topics in Nonisolated Converters ........ 15
       1.8.5.1  Nonideal Power Elements ........................ 15
       1.8.5.2  Synchronous Rectification ...................... 15
       1.8.5.3  Continuous Conduction Mode (CCM) and
                Discontinuous Conduction Mode (DCM) ............ 16
       1.8.5.4  Interleaving ................................... 16
       1.8.5.5  Ripples ........................................ 16
       1.8.5.6  Comparison of Nonisolated Topologies ........... 16
1.9  Topologies for Isolated Switching Converters .............. 17
     1.9.1  Flyback Converters ................................. 17
     1.9.2  Forward Converters ................................. 18
     1.9.3  Full-Bridge Converters ............................. 19
     1.9.4  Half-Bridge Converters ............................. 21
     1.9.5  Push-Pull Converters ............................... 21
     1.9.6  Additional Topics in Isolated DC/DC Converters ..... 22
       1.9.6.1  Synchronous Rectification of Isolated DC/DC
                Converters ..................................... 22
       1.9.6.2  Power MOSFET Parallel Body Diode Conduction .... 22
       1.9.6.3  Transformer Utilization ........................ 23
       1.9.6.4  Voltage Stress on the Active Power Transistor .. 23
     1.9.7  Comparison of Isolated DC/DC Converter Topologies .. 24
1.10 SPICE Circuit Simulation .................................. 24
1.11 Power Management Systems for Battery-Powered Devices ...... 25
1.12 Summary ................................................... 26

Chapter 2  Power Converters and Power Management ICs ........... 27
2.1  Dynamic Voltage Scaling for VLSI Power Management ......... 27
2.2  Integrated DC/DC Converters ............................... 29
     2.2.1  Segmented Output Stage ............................. 31
     2.2.2  Transient Suppression with an Auxiliary Stage ...... 34
2.3  Summary ................................................... 38

Chapter 3  Semiconductor Industry and More than Moore .......... 39
3.1  Semiconductor Industry .................................... 39
3.2  History of the Semiconductor Industry ..................... 39
     3.2.1  A Brief Timeline ................................... 39
     3.2.2  The Traitorous Eight ............................... 39
     3.2.3  Historical Road Map of the Semiconductor Industry .. 39
3.3  Food Chain Pyramid of the Semiconductor Industry .......... 42
     3.3.1  Level 1: Wafer and EDA Tools ....................... 42
     3.3.2  Level 2: Device Engineering ........................ 43
     3.3.3  Level 3: 1С Design ................................. 44
     3.3.4  Level 4: Manufacturing, Packaging, and Testing ..... 44
     3.3.5  Level 5: Systems and Software ...................... 45
     3.3.6  Level 6: Marketing and Sales ....................... 45
3.4  Semiconductor Companies ................................... 46
3.5  More than Moore ........................................... 47

Chapter 4  Smart Power 1С Technology ........................... 51
4.1  Smart Power 1С Technology Basics .......................... 51
4.2  Smart Power 1С Technology: Historical Perspective ......... 51
4.3  Smart Power 1С Technology: Industrial Perspective ......... 54
     4.3.1  Engineering Groups of a Smart Power 1С Technology .. 54
       4.3.1.1  Process Integration ............................ 54
       4.3.1.2  TCAD Support ................................... 55
       4.3.1.3  Compact Modeling ............................... 55
       4.3.1.4  Device Design .................................. 55
       4.3.1.5  ESD Design ..................................... 55
       4.3.1.6  Process Design Kit ............................. 56
       4.3.1.7  1С Design Group ................................ 56
       4.3.1.8  Reliability Group .............................. 56
       4.3.1.9  Packaging ...................................... 56
     4.3.2  Smart Power 1С Technology Development Flow ......... 56
     4.3.3  Planning Stage ..................................... 56
     4.3.4  Process Integration and Device Design .............. 57
     4.3.5  Layout, Tape-Out, Fabrication, and Test ............ 60
     4.3.6  Reliability and Qualification ...................... 60
     4.3.7  Survey of Current Smart Power Technology ........... 61
4.4  Smart Power 1С Technology: Technological Perspective ...... 62
     4.4.1  Devices for Smart Power Technology ................. 62
     4.4.2  Design Considerations for Smart Power 1С
            Technology ......................................... 63
       4.4.2.1  Power MOSFETs .................................. 63
       4.4.2.2  LIGBTs ......................................... 64
       4.4.2.3  Analog Active Devices .......................... 64
       4.4.2.4  Resistors ...................................... 65
       4.4.2.5  Capacitors ..................................... 65
       4.4.2.6  Voltage and Frequency Trims .................... 65
       4.4.2.7  Logic/Digital NMOS and PMOS .................... 65
       4.4.2.8  System-Level Design and Fabrication
                Considerations ................................. 65
     4.4.3  Isolation Methods .................................. 66

Chapter 5  Introduction to TCAD Process Simulation ............. 67
5.1  Overview .................................................. 67
5.2  Mesh Setup and Initialization ............................. 67
5.3  Ion Implantation .......................................... 69
     5.3.1  Analytical Models .................................. 69
     5.3.2  Multiple-Layer Implantation ........................ 70
     5.3.3  Monte Carlo Simulation ............................. 70
5.4  Deposition ................................................ 72
5.5  Oxidation ................................................. 72
     5.5.1  Dry Oxidation ...................................... 73
     5.5.2  Wet Oxidation ...................................... 73
     5.5.3  Oxidation Models ................................... 73
       5.5.3.1  Moving Boundaries .............................. 73
       5.5.3.2  2D Analytical Models ........................... 74
       5.5.3.3  Numerical Models ............................... 74
       5.5.3.4  LOCOS Growth Example ........................... 75
5.6  Etching ................................................... 75
5.7  Diffusion ................................................. 77
     5.7.1  Diffusion Mechanisms ............................... 77
       5.7.1.1  Direct Diffusion Mechanism ..................... 77
       5.7.1.2  Vacancy Mechanism .............................. 77
       5.7.1.3  Interstitials Mechanism ........................ 77
     5.7.2  Diffusion Models ................................... 78
       5.7.2.1  Fermi Diffusion Model .......................... 78
       5.7.2.2  Two-Dimensional Diffusion Model ................ 78
       5.7.2.3  Fully Coupled Diffusion Model .................. 78
       5.7.2.4  Steady-State Diffusion Model ................... 79
       5.7.2.5  Oxide Enhanced (Retarded) Diffusion ............ 79
5.8  Segregation ............................................... 80
5.9  Process Simulator Models Calibration ...................... 82
5.10 Introduction to 3D TCAD Process Simulation ................ 82
5.11 GPU Simulation ............................................ 84

Chapter 6  Introduction to TCAD Device Simulation .............. 87
6.1  Overview .................................................. 87
6.2  Basics about Device Simulation ............................ 87
     6.2.1  Drift-Diffusion Model .............................. 87
     6.2.2  Discretization ..................................... 87
     6.2.3  Newton's Method .................................... 88
     6.2.4  Initial Guess and Adaptive Bias Stepping ........... 89
     6.2.5  Convergence Issues ................................. 90
     6.2.6  Boundary Conditions ................................ 91
       6.2.6.1  Ohmic Contact .................................. 91
       6.2.6.2  Schottky Contacts .............................. 91
       6.2.6.3  Neumann Boundaries ............................. 92
       6.2.6.4  Lumped Elements ................................ 92
     6.2.7  Transient Simulation ............................... 92
     6.2.8  Mesh Issues ........................................ 93
6.3  Physical Models ........................................... 93
     6.3.1  Carrier Statistics ................................. 93
     6.3.2  Incomplete Ionization of Impurities ................ 93
     6.3.3  Heavy Doping Effect ................................ 94
     6.3.4  SRH and Auger Recombination ........................ 94
     6.3.5  Avalanche Breakdown and Impact Ionization .......... 94
       6.3.5.1  Avalanche Breakdown ............................ 94
       6.3.5.2  Impact Ionization Coefficients ................. 95
       6.3.5.3  Chynoweth's Law ................................ 95
       6.3.5.4  Baraff Model ................................... 96
       6.3.5.5  Fulop's Approximation .......................... 96
       6.3.5.6  Okuto-Crowell Model ............................ 96
       6.3.5.7  Lackner Model .................................. 96
       6.3.5.8  Mean Free Path Model ........................... 97
       6.3.5.9  Multiplication Factor and Ionization Integral .. 98
       6.3.5.10 Critical Electric Field ........................ 99
       6.3.5.11 Analytical Breakdown Voltage .................. 100
       6.3.5.12 Benchmark Comparison of Avalanche Breakdown
                Models ........................................ 100
     6.3.6  Carrier Mobility .................................. 100
       6.3.6.1  Models Overview ............................... 101
       6.3.6.2  Constant Mobility ............................. 101
       6.3.6.3  Two-Piece Mobility Model ...................... 102
       6.3.6.4  Canali or Beta Model .......................... 102
       6.3.6.5  Transferred Electron Model .................... 102
       6.3.6.6  Poole-Frenkel Field Enhanced Mobility Model ... 102
       6.3.6.7  Impurity Dependence of the Low Field
                Mobility Model ................................ 103
       6.3.6.8  Intel's Local Field Models .................... 103
       6.3.6.9  Lombardi Model ................................ 103
       6.3.6.10 Comparison of Different Diffusion Models ...... 104
       6.3.6.11 GaN Mobility Model (MTE Model) ................ 104
     6.3.7  Thermal and Self-Heating .......................... 106
       6.3.7.1  Heat Flow and Temperature Distribution ........ 106
     6.3.8  Bandgap Narrowing Effect .......................... 107
6.4  AC Analysis .............................................. 108
     6.4.1  Introduction ...................................... 108
     6.4.2  Basic Formulas .................................... 108
     6.4.3  AC Analysis in TCAD ............................... 111
6.5  Trap Model in TCAD Simulation ............................ 112
     6.5.1  Trap-Charge States ................................ 112
     6.5.2  Trap Dynamics ..................................... 112
6.6  Quantum Tunneling ........................................ 115
     6.6.1  Importance of Quantum Tunneling for Power
            Devices ........................................... 115
     6.6.2  Basic Theory of Tunneling for TCAD Simulation ..... 116
     6.6.3  Introduction to Nonequilibrium Green's Function
            for Tunneling ..................................... 119
6.7  Device Simulator Models Calibration ...................... 119

Chapter 7. Power 1С Process Flow with TCAD Simulation ......... 121
7.1  Overview ................................................. 121
7.2  A Mock-Up Power 1С Process Flow .......................... 121
     7.2.1  Process Flow Steps ................................ 121
     7.2.2  Structure View of the Mock-Up Process Flow ........ 121
7.3  Smart Power 1С Process Flow Simulation ................... 123
     7.3.1  P-t-Substrate ..................................... 123
     7.3.2  N-t- Buried Layer ................................. 123
     7.3.3  Epitaxial Layer Growth and Deep N Link ............ 124
     7.3.4  High-Voltage Twin-Well ............................ 127
     7.3.5  P-Body Implant for n-LDMOS ........................ 128
     7.3.6  Active Area/Shallow Trench Isolation (STI) ........ 130
     7.3.7  N-Well and P-Well ................................. 134
     7.3.8  Low-Voltage Twin Wells ............................ 136
     7.3.9  Thick Gate and Thin Gate Oxide .................... 137
     7.3.10 Poly Gate ......................................... 140
     7.3.11 NLDD and PLDD ..................................... 142
     7.3.12 Sidewall Spacer ................................... 143
     7.3.13 NSD and PSD ....................................... 144
     7.3.14 Back-End of the Line .............................. 146

Chapter 8  Integrated Power Semiconductor Devices with TCAD
Simulation .................................................... 153
8.1  PN Junction Diodes ....................................... 153
     8.1.1  PN Junction Basics ................................ 153
     8.1.2  Lateral PN Junction Diode at Equilibrium .......... 154
     8.1.3  Forward Conduction (On-State) ..................... 157
     8.1.4  Reverse Bias of a PN Junction Diode ............... 159
     8.1.5  Lateral PN Junction Diode with NBL ................ 160
     8.1.6  Breakdown Voltage Enhancement of the PN Junction
            Diode ............................................. 160
       8.1.6.1  Basic Understanding of How to Improve
                Breakdown Voltage ............................. 161
       8.1.6.2  Different P-Substrate Doping for the PN
                Junction Diode without NBL .................... 163
       8.1.6.3  Breakdown Enhancement for Diode with NBL ...... 165
       8.1.6.4  Reverse Leakage Current Path with Substrate
                Contact ....................................... 168
     8.1.7  Reverse Recovery .................................. 168
       8.1.7.1  Basic Understanding of Diode Reverse
                Recovery ...................................... 168
       8.1.7.2  Diode Reverse Recovery TCAD Simulation ........ 170
       8.1.7.3  TCAD Simulations for Carrier Lifetime
                Engineering ................................... 170
     8.1.8  Schottky Diode .................................... 170
     8.1.9  Zener Diode ....................................... 174
     8.1.10 Small Signal Model for PN Junction Diode .......... 175
8.2  Bipolar Junction Transistors ............................. 177
     8.2.1  Basic Operation of NPN BJTs ....................... 178
       8.2.1.1  Simulation Structure .......................... 178
       8.2.1.2  Collector and Base Current .................... 180
       8.2.1.3  Transistor Gain and Gummel Plot ............... 180
     8.2.2  NPN BJT Breakdown ................................. 181
       8.2.2.1  BVCBO ......................................... 181
       8.2.2.2  BVEBO ......................................... 181
       8.2.2.3  BVCEO ......................................... 181
       8.2.2.4  BVCES ......................................... 183
       8.2.2.5  Comparison of the Four Types of NPN Breakdown . 184
     8.2.3  BJT I-V Family of Curves .......................... 185
     8.2.4  Kirk Effect ....................................... 186
     8.2.5  BJT Thermal Runaway and Second Breakdown
            Simulation ........................................ 187
     8.2.6  BJT Small Signal Model and Cutoff Frequency
            Simulation ........................................ 192
       8.2.6.1  Cutoff Frequency .............................. 193
8.3  LDMOS .................................................... 193
     8.3.1  Breakdown Voltage Improvement ..................... 194
       8.3.1.1  Basic LDMOS Structure with N-Type Epitaxial
                Layer (LDMOS I) ............................... 194
       8.3.1.2  LDMOS with Shielding Plate (LDMOS II) ......... 196
       8.3.1.3  LDMOS with STI in the Drain-Drift Region
                (LDMOS III) ................................... 201
       8.3.1.4  LDMOS with Both STI Oxide and Field Plate
                (LDMOS IV) .................................... 203
       8.3.1.5  LDMOS with RESURF from P-epi Layer
                (LDMOS V) ..................................... 206
       8.3.1.6  LDMOS with P-epi RESURF and STI (LDMOS VI) .... 209
       8.3.1.7  LDMOS with Double RESURF (LDMOS VII) .......... 212
       8.3.1.8  LDMOS Multiple RESURF (LDMOS VIII) ............ 218
       8.3.1.9  Comparison of 3D Surface Plot of Electric
                Field ......................................... 221
     8.3.2  Parasitic NPN BJTs in LDMOS ....................... 221
     8.3.3  LDMOS On-State Resistance ......................... 223
       8.3.3.1  Specific On-Resistance ........................ 225
       8.3.3.2  On-Resistance Contribution .................... 225
       8.3.3.3  Comparison of Breakdown Voltage and
                On-Resistance ................................. 226
     8.3.4  LDMOS Threshold Voltage ........................... 227
     8.3.5  LDMOS with Radiation Hardening Design ............. 228
     8.3.6  LDMOS I-V Family of Curves ........................ 229
     8.3.7  LDMOS Self-Heating ................................ 230
     8.3.8  LDMOS Parasitic Capacitances ...................... 232
     8.3.9  LDMOS Gate Charge ................................. 234
     8.3.10 LDMOS Undamped Inductive Switching (UIS) .......... 236
     8.3.11 Compact Models of LDMOS ........................... 237

Chapter 9  Integrated Power Semiconductor Devices with 3D
TCAD Simulations .............................................. 239
9.1  3D Device Layout Effect .................................. 239
9.2  3D Simulation of LIGBT ................................... 242
     9.2.1  About LIGBT ....................................... 242
     9.2.2  Segmented Anode LIGBT ............................. 243
     9.2.3  3D Process Simulation of Segmented Anode LIGBT .... 245
     9.2.4  3D Device Simulation of Segmented Anode LIGBT ..... 248
       9.2.4.1  Forward Characteristic Simulation ............. 248
       9.2.4.2  LIGBT Turnoff Transient Simulation ............ 251
       9.2.4.3  Forward I-V Family of Curves Comparison with
                LDMOS ......................................... 253
9.3  Super Junction LDMOS ..................................... 254
     9.3.1  Basic Concept ..................................... 254
       9.3.1.1  How to Choose the Pillar Width W^ ............. 255
       9.3.1.2  About Dose Balance ............................ 258
       9.3.1.3  On-Resistance ................................. 260
     9.3.2  Super Junction LDMOS Structure .................... 261
     9.3.3  3D Process Simulation of Super Junction LDMOS ..... 263
     9.3.4  3D Device Simulation of Super Junction LDMOS ...... 264
     9.3.5  3D Simulation of a Standard LDMOS with the Same
            N-Drift Doping .................................... 264
     9.3.6  3D Simulation of a Standard LDMOS with Reduced
            N-Drift Doping .................................... 266
     9.3.7  Comparison of Super Junction LDMOS and Standard
            LDMOS ............................................. 267
9.4  Super Junction Power FinFET .............................. 268
     9.4.1  Process Flow of the Super Junction Power FinFET ... 269
     9.4.2  Measurement Results of Super Junction Power
            FinFET ............................................ 270
     9.4.3  3D Simulation of Super Junction Power FinFET ...... 271
9.5  Large Interconnect Simulation ............................ 274
     9.5.1  3D Process Simulation of the Large Interconnect ... 275
       9.5.1.1  Substrate ..................................... 276
       9.5.1.2  Contacts ...................................... 276
       9.5.1.3  Metall ........................................ 277
       9.5.1.4  Vial .......................................... 277
       9.5.1.5  Metal2 ........................................ 277
       9.5.1.6  Via2 .......................................... 279
       9.5.1.7  Metal3 ........................................ 279
     9.5.2  3D Device Simulation of the Large Interconnect .... 280

Chapter 10 GaN Devices, an Introduction ....................... 281
10.1 Compound Materials versus Silicon ........................ 281
10.2 Substrate Materials for GaN Devices ...................... 282
10.3 Polarization Properties of Ill-Nitride Wurtzite .......... 283
     10.3.1 Microscopic Dipoles and Polarization Vector ....... 283
     10.3.2 Crystal Structure and Polarization ................ 284
     10.3.3 Ideal c0/a0 Ratio for Zero Net Polarization ....... 284
       10.3.3.1 Strain-Induced Polarization ................... 285
       10.3.3.2 Empirical Approach to Modeling Polarization ... 286
10.4 AlGaN/GaN Heterojunction ................................. 287
     10.4.1 Band Diagram Plots with a Fixed Al Mole Fraction .. 288
     10.4.2 Band Diagram Plots with a Fixed AlGaN Thickness ... 289
     10.4.3 AlGaN/GaN Structure with Doped AlGaN or GaN
            Layer ............................................. 289
     10.4.4 AlGaN/GaN Structure with Metal Contacts ........... 291
10.5 Traps in AlGaN/GaN Structure ............................. 292
10.6 A Simple AlGaN/GaN HEMT .................................. 294
     10.6.1 Device Structure .................................. 294
     10.6.2 Id-Vg, Curves for GaN HEMT ........................ 294
     10.6.3 Summary ........................................... 295
10.7 GaN Power HEMT Example ................................... 297
     10.7.1 Device Structure .................................. 297
     10.7.2 Impact Ionization Coefficient of GaN Material ..... 297
     10.7.3 Breakdown Simulation of GaN HEMT .................. 299
10.8 GaN Power HEMT Example II ................................ 300
10.9 Gate Leakage Simulation of GaN HEMT ...................... 301
     10.9.1 Device Structure .................................. 301
     10.9.2 Models and Simulation Setup ....................... 301
     10.9.3 Gate Leakage Simulation ........................... 302
       10.9.3.1 Pure TCAD Simulation .......................... 302
       10.9.3.2 TCAD Simulation with Slow Transient ........... 304
       10.9.3.3 TCAD Simulation with Equivalent Circuits ...... 304
10.10 Market Prospect of Compound Semiconductors for Power
      Applications ............................................ 305

Appendix A: Carrier Statistics ................................ 307
Appendix B: Process Simulation Source Code .................... 309
Appendix C: Trap Dynamics and AC Analysis ..................... 321
Bibliography .................................................. 323
Index ......................................................... 331


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